Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a circuit for generating or transferring a signal swinging in a current mode logic (CML) region.
In semiconductor devices, a signal swinging in a CML region (hereinafter, referred to as a CML signal) is widely used in an input/output (I/O) interface for a high frequency signal, such as a clock signal.
The CML region refers to a potential level region having a predefined range defined by a predefined DC potential level, or a potential level region having a predefined range defined by an average potential level determined by a predefined criterion. The CMS signal refers to a signal toggling at a predefined frequency between a maximum potential level (Vmax) of the CML region and a minimum potential level (Vmin) of the CML region with the center of a reference potential level in the CML region.
For example, although a level of a power supply voltage (VDD) and a level of a ground voltage (VSS) in a device for inputting/outputting a CML signal are 1.5 V and 0 V, respectively, the CML region may be defined in a range from 1.5 V to 1.0 V. A reference potential level of the CML region is 1.25 V, and the CML signal is a signal toggling at a predefined frequency in a swing range of 0.5 V with a center of 1.25 V.
As described above, the CML region is designed to have a relatively small size compared with a potential level region defined by a difference between a level of a power supply voltage (VDD) and a level of a ground voltage (VSS) in a device for inputting/outputting a CML signal. This is because the CML signal is generally a high frequency clock signal.
That is, the CML region is a region defined for transferring a clock signal stably even though the clock signal is a high frequency clock signal ranging from several GHz to several tens of GHz or more.
In semiconductor devices, a signal swinging in a CMOS region (hereinafter, referred to as a CMOS signal) is widely used in an I/O interface for a signal which determines a logic level.
The CMOS region refers to a potential level region defined by a difference between a level of a power supply voltage (VDD) and a level of a ground voltage (VSS). The CMOS signal refers to a signal toggling at a predefined frequency between a level of a power supply voltage (VDD), which is a maximum potential level (Vmax) of the CMOS region, and a level of a ground voltage (VSS), which is a minimum potential level (Vmin) of the CMOS region, with the center of half the potential level between the level of the power supply voltage (VDD) and the level of the ground voltage (VSS).
Therefore, as described above, in the case of the CML region, even though the level of the power supply voltage (VDD) and the level of the ground voltage (VSS) are 1.5 V and 0 V, respectively, the potential levels of 1.5 V and 0 V are specified as the CML region, so that the swing range of the CML signal may be 0.5 V. However, in the case of the CMOS region, when the level of the power supply voltage (VDD) and the level of the ground voltage (VSS) are 1.5 V and 0 V, respectively, the potential levels of 1.5 V and 0 V are determined as the CMOS region. Thus, the swing range of the CMOS signal is 1.5 V.
For this reason, the swing range of the CMOS signal is inevitably lager than the swing range of the CML signal. This means that the CMOS signal is suitable for use as data whose logic level is determined according to the potential level.
FIG. 1A is a circuit diagram of a circuit for shifting a voltage level of a CMOS signal in a conventional semiconductor device.
FIG. 1B is a circuit diagram of a circuit for shifting a voltage level of a CML signal in a conventional semiconductor device.
Referring to FIG. 1A, a CMOS signal CMOS_IN is inputted to inverters INV1 and INV2, which use a first power supply voltage VDD1 as a power supply voltage, and outputted as CMOS signals CMOS_IN and /CMOS_IN swinging between the first power supply voltage VDD1 and the ground voltage VSS.
The CMOS signals CMOS_IN and /CMOS_IN swinging between the first power supply voltage VDD1 and the ground voltage VSS are inputted to a voltage level shifter 100, which uses a second power supply voltage VDD2 as a power supply voltage, and outputted as CMOS signals CMOS_OUT and /CMOS_OUT swinging between the second power supply voltage VDD2 and the ground voltage VSS.
The operation of the voltage level shifter 100 will be described below in more detail. The voltage level shifter 100 performs an operation of making the voltage levels at CMOS signal output terminals CMOS_OUT_ND and /CMOS_OUT_ND swing in the CMOS region between the second power supply voltage VDD2 and the ground voltage VSS by controlling the CMOS signal output terminals CMOS_OUT_ND and /CMOS_OUT_ND in response to the CMOS signals CMOS_IN and /CMOS_IN. The CMOS signal output terminals CMOS_OUT_ND and /CMOS_OUT_ND are connected to drains of the NMOS transistors MN1 and MN2, respectively, and the ground voltage (VSS) terminal is connected to sources of the NMOS transistors MN1 and MN2. The CMOS signals CMOS_IN and /CMOS_IN swing between the first power supply voltage VDD1 and the ground voltage VSS, and are inputted to gates of the NMOS transistors MN1 and MN2.
In this case, the swing range is sufficiently wide. This can be seen from the fact that the CMOS signals CMOS_IN and /CMOS_IN, swinging between the first power supply voltage VDD1 and the ground voltage VSS and being inputted to the gates of the NMOS transistors MN1 and MN2, swing in the CMOS region. Thus, the NMOS transistors MN1 and MN2 provided in the voltage level shifter 100 may operate normally, without any problems.
Therefore, the voltage level shifter 100 having the configuration of FIG. 1A may perform the power supply voltage level shifting operation normally, whether the level of the first power supply voltage VDD1 is higher or lower than the level of the second power supply voltage VDD2.
Referring to FIG. 1B, a CML buffer 120, which uses the first supply voltage VDD1 as a power supply voltage, receives CML signals CML_IN and /CML_IN to generate CML signals CML_TRANS and /CML_TRANS swinging with the center at a first voltage level lower than the first power supply voltage VDD1 by a set voltage level.
Since the CML signal has a narrow swing range as described above, the first voltage level lower than the first power supply voltage VDD1 by the set voltage level is expected to be higher than a voltage level of ½*VDD1. Therefore, the swing centers of the CML signals CML_TRANS and /CML_TRANS, outputted from the CML buffer 120 using the first power supply voltage VDD1 as the power supply voltage, are expected to lean toward the voltage level of the first power supply voltage VDD1.
The operation of the CML buffer 120 using the first power supply voltage VDD1 as the power supply voltage will be described below in more detail. When the CML input signals CML_IN and /CML_IN inputted to the CML buffer 120 have a swing range enough to turn on/off the NMOS transistors MN1 and MN2 provided in the CML buffer 120, it is possible to generate the CML signals CML_TRANS and /CML_TRANS swinging around the first voltage level lower than the voltage level of the first power supply voltage VDD1 by the set voltage level, while alternately turning on/off the NMOS transistors MN1 and MN2 provided in the CML buffer 120.
The CML signals CML_TRANS and /CML_TRANS swinging around the first voltage level lower than the voltage level of the first power supply voltage VDD1 by the set voltage level are inputted to the CML buffer 140, which uses the second power supply voltage VDD2 as the power supply voltage. The CML buffer outputs the CML signals CML_OUT and /CML_OUT, which swing around the second voltage level lower than the voltage level of the second power supply voltage VDD2 by the set voltage level, and are generated through the same operation as the CML buffer 120. In this way, the power supply voltage level shifting operation is completed.
In the power supply voltage level shifting circuit having the configuration of FIG. 1B, however, the power supply voltage level shifting operation may not be normally performed according to the relationship between the level of the first power supply voltage VDD1 and the level of the second power supply voltage VDD2.
That is, when the level of the first power supply voltage VDD1 is lower than the level of the second power supply voltage VDD2, the CML signals CML_TRANS and /CML_TRANS outputted from the CML buffer 120 using the first power supply voltage VDD1 can have a swing range large enough to turn on/off the NMOS transistors MN3 and MN4 provided in the CML buffer 140 using the second power supply voltage VDD2. Thus, the power supply voltage level shifting operation may be performed without any problems.
However, when the level of the first power supply voltage VDD1 is higher than the level of the second power supply voltage VDD2, the CML signals CML_TRANS and /CML_TRANS outputted from the CML buffer 120 using the first power supply voltage VDD1 may not have a swing range large enough to turn on/off the NMOS transistors MN3 and MN4 provided in the CML buffer 140 using the second power supply voltage VDD2. Thus, the power supply voltage level shifting operation may not be performed.
For example, it is assumed that the level of the first power supply voltage VDD1 is 2.1 V, the level of the second power supply voltage VDD2 is 1.2 V, the swing range of the CML signals CML_TRANS and /CML_TRANS outputted from the CML buffer 120 using the first power supply voltage VDD1 is 0.4 V (range of 2.1 V to 1.7 V), and the threshold voltages (Vth) provided in the NMOS transistors MN3 and MN4 of the CML buffer 140 using the second power supply voltage VDD2 are 0.4 V. In this case, in order to make a current flow between the drains and the sources of the NMOS transistors MN3 and MN4 provided in the CML buffer 140 using the second power supply voltage VDD2, the voltage levels of the source terminals must be lower than the voltage levels of the drain terminals. The voltage levels of the drain terminals must be 1.2 V and the voltage levels of the source terminals must be 0.8 V. However, since the swing range of the CML signals CML_TRANS and /CML_TRANS outputted from the CML buffer 120 using the first power supply voltage VDD1 and inputted to the gates of the NMOS transistors MN3 and MN4 are in a range from 2.1 V to 1.7 V, a current always flows between the drains and the sources of the NMOS transistors MN3 and MN4 provided in the CML buffer 140 using the second power supply voltage VDD2, without regard to the variation in the levels of the CML signals CML_TRANS and /CML_TRANS. Hence, the CML output signals CML_OUT and /CML_OUT do not swing, but always maintain the level of 0.8 V.
The power supply voltage level shifting circuit having the configuration of FIG. 1B has not been practically used because the power supply voltage level shifting operation may not be normally performed according to the relationship between the level of the first power supply voltage VDD1 and the level of the second power supply voltage VDD2. Therefore, the level shifter having the configuration of FIG. 1A is embedded into the level shifter having the configuration of FIG. 1B in order to perform the power supply voltage level shifting operation successfully.
That is, in order to shift the levels of the CML signals, the CML signals are converted into the CMOS signals, level-shifted in the CMOS region, and then again converted into the CML signals.
However, if the swing region is converted several times, jitters may occur in the signals during the conversion operations, or a duty ratio may be changed. Consequently, the semiconductor devices using the final CML output signal may not operate normally.